1. Field of the Invention
The present invention relates to a semiconductor device having an SOI structure and a method of manufacturing the semiconductor device.
2. Description of the Background Art
Attention has recently been paid to a semiconductor device referred to as an SOI (Silicon-On-Insulator) device to be a high-speed device having low power consumption.
The SOI device is fabricated on an SOI substrate having an SOI structure in which a buried oxide film is interposed between an SOI layer and a silicon substrate. In particular, an SOI device in which an SOI layer to be an upper silicon layer has a small thickness (up to approximately several xcexcm) is referred to as a thin film SOI device to which attention has been paid and has been expected for application to an LSI for mobile equipment. Conventionally, an SOI element (a (semiconductor) element formed on an SOI layer having an SOI structure) penetrates through Si (silicon) of the SOI layer and is completely isolated through an oxide film for isolation formed over the buried oxide film.
The complete isolation technique is characterized by being latch up free (latch-up is not caused), and resistant to noise and the like because the element is electrically isolated completely from other elements. However, since a transistor is operated in an electrical floating state, there is a problem in that a frequency dependency is caused on a delay time and a floating-body effect, for example, a kink effect in which a hump is generated on a drain current-drain voltage characteristic or the like. In order to suppress the floating-body effect, an isolation oxide film (partial oxide film) is formed in an upper layer portion so as not to come in contact with the buried oxide film and constitutes a partial isolation region together with a part of an SOI layer in a lower layer portion and a body terminal is provided in a body region formed in a region isolated in the partial isolation region. Consequently, a partial isolation technique capable of fixing a substrate potential (body potential) through the SOI layer provided under the partial oxide film is effective. However, there is a problem in that the partial isolation technique does not have the latch up free which is the advantage of the complete isolation technique.
Therefore, there has been developed a partial isolation and complete isolation combination technique having both advantages. In the partial and complete isolation combination technique, trench depths are varied for the partial isolation and complete isolation combination. For this reason, after an oxide film of an isolation oxide film is provided and is then subjected to a CMP processing, dishing is generated in a complete isolation portion having a great trench depth differently from the partial isolation. Accordingly, there is a problem in that the shape of an important isolation edge for the reliability of a gate oxide film is varied between the partial isolation and the complete isolation. In the combination process, moreover, the isolation edge of the complete isolation is lowered so that a threshold voltage of a MOS transistor is locally dropped in an edge portion. Therefore, there is a problem in that a leakage current might be increased.
In only the conventional device, moreover, a distance from the body terminal is varied for each transistor. Therefore, there is a problem in that a body resistance is varied, resulting in a variation in a threshold voltage.
In addition, there is a problem in that a body potential cannot always be fixed with a high stability by the partial isolation technique for fixing the body potential through the SOI layer provided under the partial oxide film.
A first aspect of the present invention is directed to a semiconductor device including an SOI structure having a semiconductor substrate, a buried insulating layer and an SOI layer, comprising a MOS transistor provided in an element formation region of the SOI layer, and a partial isolation region provided in the SOI layer and serving to isolate the element formation region, the partial isolation region including a partial insulating film provided in an upper layer portion of the SOI layer and a partial insulating film lower semiconductor region to be a part of the SOI layer present in a lower layer portion of the SOI layer, the MOS transistor including source and drain regions of a first conductivity type selectively formed in the SOI layer, respectively, a gate electrode having a gate electrode main part formed through a gate oxide film on a region of the SOI layer between the source and drain regions, and a body region having a body region main part to be a region of a second conductivity type of the SOI layer between the source and drain regions and a body region potential setting portion electrically connected from the body region main part in the element formation region and capable of externally fixing an electric potential.
A second aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the body region potential setting section includes a body region source/drain adjacent portion in a gate width direction adjacently to the source and drain regions and extended in a gate length direction from the body region main part, and the gate electrode further has a gate extension region extended in the gate length direction from an end of the gate electrode main part and formed on a part of the body region source/drain adjacent portion, and serving to electrically block the body region source/drain adjacent portion and the source and drain regions through the gate extension region.
A third aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, wherein the body region source/drain adjacent portion includes a first body region source/drain adjacent portion extended in a first direction from the body region main part and a second body region source/drain adjacent portion extended in a second direction opposite to the first direction from the body region main part, and the gate extension region includes a first gate extension region formed on a vicinity of the first body region source/drain adjacent portion and a second gate extension region extended on the second body region source/drain adjacent portion.
A fourth aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, wherein the body region source/drain adjacent portion includes one body region source/drain adjacent portion, and the gate extension region includes one gate extension region formed on a vicinity of the body region source/drain adjacent portion.
A fifth aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, wherein the body region source/drain adjacent portion has a high concentration region having a higher impurity concentration of a second conductivity type than that in other regions over a region provided apart from the gate extension region by a predetermined distance.
A sixth aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, wherein the gate extension region includes a gate extension region having an impurity concentration of the second conductivity type of 5xc3x971018 cmxe2x88x923 or less.
A seventh aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the body region potential setting portion includes a semiconductor region for body fixation of the second conductivity type formed together with the source region.
An eighth aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the partial isolation film lower semiconductor region has the second conductivity type and is formed in contact with the body region, the semiconductor device further comprising an element formation region outside body region of a first conductivity type provided outside the element formation region of the SOI layer and being capable of externally fixing an electric potential, the element formation region outside body region being formed in contact with the partial insulating film lower semiconductor region.
A ninth aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the source and drain regions have such depths as to reach the buried insulating layer.
A tenth aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the source and drain regions have such depths that a depletion layer extended from the source and drain regions does not reach the buried insulating layer during a normal operation.
An eleventh aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the source and drain regions have such depths that the buried insulating layer is not reached and a depletion layer extended from the drain region reaches the buried insulating layer during a normal operation.
A twelfth aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the drain region has a greater depth than that of the source region and has such a depth that a depletion layer extended from the drain region reaches the buried insulating layer during a normal operation.
A thirteenth aspect of the present invention is directed to a semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer and an SOI layer, comprising first and second semiconductor regions of a predetermined conductivity type provided in an element formation region of the SOI layer, and a partial insulating film provided in an upper layer portion of the element formation region and a partial insulating film lower semiconductor region of a predetermined conductivity type to be a part of the element formation region in a lower layer portion of the element formation region, wherein the partial insulating film lower semiconductor region is electrically connected to the first and second semiconductor regions to constitute a resistive element.
A fourteenth aspect of the present invention is directed to the semiconductor device according to the thirteenth aspect of the present invention, further comprising a complete insulating film provided through the SOI layer for isolating the element formation region.
A fifteenth aspect of the present invention is directed to the semiconductor device according to the thirteenth aspect of the present invention, wherein the element formation region other than the partial insulating film and the first and second semiconductor regions is a part of a region where the resistive element is to be formed.
A sixteenth aspect of the present invention is directed to the semiconductor device according to the thirteenth aspect of the present invention, wherein the resistive element includes a load resistor of an SRAM memory cell.
A seventeenth aspect of the present invention is directed to a semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer and an SOI layer, comprising first and second element formation regions provided in the SOI layer, a partial isolation region including a partial insulating film provided in an upper layer portion of the SOI layer and a semiconductor region to be a part of the SOI layer which is provided under the partial insulating film and serving to isolate the first and second element formation regions from each other, and first and second MOS transistors formed in the first and second element formation regions, respectively, wherein at least one of a structure of a body region, a structure of a gate electrode and presence/absence of body potential fixation in the first and second MOS transistors is varied to make transistor characteristics of the first and second MOS transistors different from each other.
An eighteenth aspect of the present invention is directed to a semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer and an SOI layer, comprising first and second element formation regions provided in the SOI layer, a partial isolation region including a partial insulating film provided in an upper layer portion of the SOI layer and a semiconductor region to be a part of the SOI layer which is provided under the partial insulating film and serving to isolate the first element formation region from other regions, a complete isolation region including a complete insulating film provided through the SOI layer and serving to isolate the second element formation region from other regions, a first MOS transistor formed in the first element formation region, and a second MOS transistor formed in the second element formation region, wherein the first and second MOS transistors have different transistor characteristics.
A nineteenth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of (a) preparing an SOI substrate including an SOI structure having a semiconductor substrate, a buried insulating layer and an SOI layer, (b) selectively forming a partial insulating film in an upper layer portion of the SOI layer, the partial insulating film constituting a partial isolation region for isolating first and second element isolation regions in the SOI layer together with a semiconductor region to be a part of the SOI layer which is provided under the partial insulating film, and (c) forming first and second MOS transistors in the first and second element formation regions, wherein at the step (c), at least one of a structure of a body region, a structure of a gate electrode and presence/absence of body potential fixation in the first and second MOS transistors is varied to make transistor characteristics of the first and second MOS transistors different from each other.
A twentieth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of (a) preparing an SOI substrate including an SOI structure having a semiconductor substrate, a buried insulating layer and an SOI layer, (b) selectively forming a partial insulating film in an upper layer portion of the SOI layer, the partial insulating film constituting a partial isolation region for isolating the first element isolation region from other regions together with a semiconductor region to be a part of the SOI layer which is provided under the partial insulating film, (c) selectively forming a complete insulating film through the SOI layer, the complete isolating film constituting a complete isolation region for isolating the second element formation region from other regions, (d) forming a first MOS transistor in the first element formation region, and (e) forming a second MOS transistor in the second element formation region, wherein the steps (d) and (e) are performed such that the first and second MOS transistors have different transistor characteristics.
According to the first aspect of the present invention, the body region potential setting portion capable of externally fixing an electric potential is provided in the element formation region. Therefore, it is possible to fix a body potential to be an electric potential of the body region main part with a high stability.
According to the second aspect of the present invention, the body region source/drain adjacent portion and the source and drain regions are electrically blocked by the gate extension region of the gate electrode. Consequently, the presence of the body region source/drain adjacent portion does not affect the operation of the MOS transistor and the body potential can be fixed with a high stability.
According to the third aspect of the present invention, the body potential can be fixed in the first and second body region source/drain adjacent portions, respectively. Correspondingly, it is possible to fix the body potential with a higher stability.
According to the fourth aspect of the present invention, it is possible to fix the body potential with a high stability by one body region source/drain adjacent portion while minimizing a gate capacitance in one gate extension region.
According to the fifth aspect of the present invention, the body region source/drain adjacent portion has a high concentration region having a higher impurity concentration than that in other regions over the region provided apart from the gate extension region by a predetermined distance. Therefore, when the impurity of the second conductivity type for the formation of a high concentration region is to be implanted, it is possible to reliably prevent the impurity of the second conductivity type from being implanted into the gate extension region.
According to the sixth aspect of the present invention, the gate extension region includes a gate extension region having an impurity concentration of the second conductivity type of 5xc3x971018 cmxe2x88x923 or less. Therefore, it is possible to prevent a threshold voltage of the MOS transistor from being varied.
According to the seventh aspect of the present invention, the electric potential is fixed in the semiconductor region for body potential fixation of the second conductivity type which is formed together with the source region. Consequently, it is possible to fix the body potential with a high stability. The presence of the semiconductor region for body potential fixation does not affect the MOS transistor for being operated by setting the body region and the source region to have the same electric potential.
According to the eighth aspect of the present invention, it is possible to fix the electric potential of the body region from the element formation region outside body region through the partial isolating film lower semiconductor region in addition to the body region potential setting portion.
According to the ninth aspect of the present invention, the source and drain regions in the MOS transistor have such depths as to reach the buried insulating layer. Therefore, a pn junction is not formed on respective bottom faces. Consequently, a junction leakage can be suppressed.
According to the tenth aspect of the present invention, the source and drain regions in the MOS transistor have such depths that the depletion layer extended from the source and drain regions does not reach the buried insulating layer during the normal operation. Therefore, in the case in which the electric potential of the body region is to be fixed on the outside of the element formation region, the body potential fixation can be carried out with a high stability.
According to the eleventh aspect of the present invention, the source and drain regions in the MOS transistor do not reach the buried insulating layer and the depletion layer extended from the drain region has such a depth as to reach the buried insulating layer during the normal operation. Therefore, it is possible to fix the body potential on the outside of the element formation region while reducing a junction capacitance.
According to the twelfth aspect of the present invention, the drain region has a greater depth than that of the source region and has such a depth that a depletion layer extended from the drain region reaches the buried insulating layer during a normal operation. Therefore, it is possible to reduce a junction capacitance in the drain region while fixing the body potential through the source region on the outside of the element formation region.
According to the thirteenth aspect of the present invention, the partial insulating film lower semiconductor region of a predetermined conductivity type to be a part of the SOI layer provided under the partial insulating film is a component of a resistive element. Therefore, it is possible to obtain a resistive element having a high resistance value with a comparatively small formation area. As a result, it is possible to constitute a semiconductor integrated circuit having a high degree of integration.
According to the fourteenth aspect of the present invention, it is possible to completely isolate the resistive element from the outside through the complete insulating film.
According to the fifteenth aspect of the present invention, the element formation region other than the partial insulating film and the first and second semiconductor regions is a part of a region where the resistive element is to be formed. Consequently, it is possible to prevent the resistance value of the resistive element from being varied.
According to the sixteenth aspect of the present invention, the resistive element is used as the load resistor of an SRAM. Consequently, it is possible to constitute an SRAM having a high degree of integration.
According to the seventeenth aspect of the present invention, at least one of a structure of a body region, a structure of a gate electrode and presence of body potential fixation in the first and second MOS transistors is varied to make transistor characteristics of the first and second MOS transistors different from each other. Consequently, it is possible to constitute a high functional semiconductor integrated circuit comprising first and second MOS transistors.
According to the eighteenth aspect of the present invention, the transistor characteristic is varied between the first MOS transistor isolated by the partial isolation region and the second transistor isolated by the complete isolation region. Consequently, it is possible to constitute a high functional semiconductor integrated circuit comprising first and second MOS transistors.
According to the nineteenth aspect of the present invention, at least one of a structure of a body region, a structure of a gate electrode and presence of body potential fixation in the first and second MOS transistors is varied to make transistor characteristics of the first and second MOS transistors different from each other. Consequently, it is possible to constitute a high functional semiconductor integrated circuit comprising first and second MOS transistors.
According to the twentieth aspect of the present invention, the transistor characteristic is varied between the first MOS transistor isolated by the partial isolation region and the second transistor isolated by the complete isolation region. Consequently, it is possible to constitute a high functional semiconductor integrated circuit comprising first and second MOS transistors.
In order to solve the above-mentioned problems, it is an object of the present invention to provide a semiconductor device having an SOI structure which can fix a body potential with a high stability in a body region over an element formation region isolated by a partial isolation region and a semiconductor device capable of constituting a high functional semiconductor integrated circuit for a partial isolation or a partial isolation and complete isolation combination, and a method of manufacturing the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.